the puma68s4000/a is a 4mbit cmos high speed static ram organised as 128k x 32 in a jedec 68 pin surface mount plcc, available with access times of 20, 25, 35, and 45ns. the output width is user configurable as 8 , 16 or 32 bits using four chip selects (cs1~4). the device features multiple ground pins for maximum noise immunity and ttl compatible inputs and outputs. the puma 68s4000/a offers a dramatic space saving advantage over four standard 128kx8 devices. address inputs a0 - a16 a0 - a16 a0 - a16 a0 - a16 a0 - a16 data input/output d0 - d31 d0 - d31 d0 - d31 d0 - d31 d0 - d31 chip select cs1~4 cs1~4 cs1~4 cs1~4 cs1~4 write enable we1~4 we1~4 we1~4 we1~4 we1~4 output enable oe oe oe oe oe no connect nc nc nc nc nc power (+5v) v v v v v cc cc cc cc cc ground gnd gnd gnd gnd gnd package details package details package details package details package details block diagram block diagram block diagram block diagram block diagram (puma 68 s4000a page 2) pin functions pin functions pin functions pin functions pin functions pin definition pin definition pin definition pin definition pin definition (puma 68 s4000a page 2) description features features features features features 128k x 32 sram module 128k x 32 sram module 128k x 32 sram module 128k x 32 sram module 128k x 32 sram module puma 68s4000/a - 020/025/35/45 puma 68s4000/a - 020/025/35/45 puma 68s4000/a - 020/025/35/45 puma 68s4000/a - 020/025/35/45 puma 68s4000/a - 020/025/35/45 issue 4.4 : december 1999 plastic 68 j-leaded jedec plcc d0 d1 d2 d3 d4 d5 d6 d7 gnd d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 gnd d24 d25 d26 d27 d28 d29 d30 d31 nc a0 a1 a2 a3 a4 a5 gnd a6 a8 a10 vcc cs3 cs4 we 9 8 7 6 5 4 3 2 1 6867666564636261 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 oe cs2 nc nc nc nc vcc a11 a12 a13 a14 cs1 nc nc puma 68s4000 view from above a9 a7 gnd a15 a16 d16-23 d0-7 d8-15 d24-31 cs1 cs2 cs3 cs4 oe we a0-a16 128kx8 sram 128kx8 sram 128kx8 sram 128kx8 sram elm road, west chirton, north shields, tyne & wear ne29 8se, england tel.+44 (0191) 2930500 fax.+44 (0191) 2590997 ? fast access times of 20 ,25, 35 and 45 ns. ? jedec 68 'j' leaded plastic surface mount substrate ? industrial or military grade. ? upgradeable footprint. ? user configurable as 8 / 16 / 32 bit wide output. ? operating power (32-bit) 4.00 w (max) low power standby (ttl) 1.43 w (max) -l version (cmos) 44 mw (max) ? fully static operation. ? multiple ground pins for maximum noise immunity. ? single 5v 10% power supply.
puma 68s4000/a - 020/025/35/45 issue 4.4 : december 1999 2 puma 68 s4000a pinout and block diagram. 128k x 8 sram 128k x 8 sram 128k x 8 sram 128k x 8 sram a0 ~a16 /oe /we4 /we3 /we2 /we1 /cs1 /cs2 /cs3 /cs4 d0~7 d8~15 d16~23 d24~31 d0 d1 d2 d3 d4 d5 d6 d7 gnd d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 gnd d24 d25 d26 d27 d28 d29 d30 d31 nc a0 a1 a2 a3 a4 a5 gnd a6 a7 a8 a9 a10 vcc /cs3 /cs4 /we1 9876543216867666564636261 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 /oe /cs2 /we2 /we3 /we4 nc gnd vcc a11 a12 a13 a14 a15 a16 /cs1 nc nc puma 68s4000a view from above
puma 68s4000/a - 020/025/35/45 issue 4.4 : december 1999 3 voltage on any pin relative to v ss v t (2) -0.5 - 7.0 v power dissipation p t - - 4.0 w storage temperature t stg -65 - 150 o c notes : (1) stresses above those listed may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (2) v t can be -3.0v pulse of less than 10ns. dc operating conditions dc operating conditions dc operating conditions dc operating conditions dc operating conditions parameter symbol min typ max unit absolute maximum ratings absolute maximum ratings absolute maximum ratings absolute maximum ratings absolute maximum ratings (1) recommended operating conditions recommended operating conditions recommended operating conditions recommended operating conditions recommended operating conditions parameter symbol min typ max unit supply voltage v cc 4.5 5.0 5.5 v input high voltage v ih 2.2 - v cc +0.3 v input low voltage v il -0.3 - 0.8 v operating temperature (commercial) t a 0 - 70 o c (industrial) t ai -40 - 85 o c (suffix i) (military) t am -55 - 125 o c (suffix m) parameter symbol test condition min typ max unit input leakage current i li1 v in =0v to v cc -20 - 20 a output leakage current i lo v i/o =0v to v cc -40 - 40 a operating supply current (2) 32 bit i cc32 cs (1) =v il , i i/o =0ma, f=f max - - 840 ma 16 bit i cc16 as above. - - 540 ma 8 bit i cc8 as above. - - 400 ma standby supply current (ttl) i sb cs (1) =v ih , f=f max , v in =v il or v ih - - 260 ma -l version (cmos) i sb1 cs 3 v cc -0.2v, 0.2v 3 v in 3 v cc -0.2v,f=0 - - 8 ma output voltage low v ol i ol = 8.0ma,v cc =min - - 0.4 v output voltage high v oh i oh = -4.0ma,v cc =min 2.4 - - v notes: (1) cs1~4 inputs operate simultaneously for 32 bit mode, in pairs for 16 bit mode and singly for 8 bit mode. (2) at f=f max address and data inputs are cycling at max frequency. dc electrical characteristics dc electrical characteristics dc electrical characteristics dc electrical characteristics dc electrical characteristics (v cc =5v10%, t a = -55 o c to +125 o c)
puma 68s4000/a - 020/025/35/45 issue 4.4 : december 1999 4 capacitance capacitance capacitance capacitance capacitance (v cc =5v10%,t a =25 o c) note: capacitance calculated, not measured. parameter symbol test condition min typ max unit input capacitance address,oe,we c in1 v in =0v - - 34 pf output capacitance 8-bit mode (worst case) c i/o v i/o =0v - - 42 pf * input pulse levels: 0v to 3.0v * input rise and fall times: 3ns * input and output timing reference levels: 1.5v * output load: see diagram * v cc =5v10% ac test conditions ac test conditions ac test conditions ac test conditions ac test conditions output load output load output load output load output load operation truth table operation truth table operation truth table operation truth table operation truth table cs1 cs2 cs3 cs4 oe we supply current mode lhhhxl i cc8 write d 0~7 hl hhxl i cc8 write d 8~15 hh lhxl i cc8 write d 16~23 hh hlxl i cc8 write d 24~31 llhhxl i cc16 write d 0~15 hh llxl i cc16 write d 16~31 ll llxl i cc32 write d 0~31 lhhhlh i cc8 read d 0~7 hl hhlh i cc8 read d 8~15 hh lhlh i cc8 read d 16~23 hh hllh i cc8 read d 24~31 llhhlh i cc16 read d 0~15 hh lllh i cc16 read d 16~31 ll lllh i cc32 read d 0~31 xx xxhh i cc32 /i cc16 /i cc8 d 0~31 high-z hh hhxx i sb ,i sb1 d 0~31 standby notes : h = v ih : l =v il : x = v ih or v il parameter symbol test condition min typ max unit v cc for data retention v dr cs=v cc -0.2v 2.0 - - v data retention current i ccdr1 (1) v cc = 2.0v, cs > v cc -0.2v, v in >0v - - 2.2 ma data retention time t cdr see retention waveform 0--ns operation recovery time t r see retention waveform t rc --ns low vcc data retention characteristics - l version only 166w 30pf i/o pin 1.76v
puma 68s4000/a - 020/025/35/45 issue 4.4 : december 1999 5 write cycle write cycle write cycle write cycle write cycle -020 -025 -35 -45 parameter symbol min max min max min max min max unit write cycle time t wc 20 - 25 - 35 - 45 - ns chip selection to end of write t cw 15 - 20 - 25 - 35 - ns address valid to end of write t aw 15 - 20 - 25 - 35 - ns address setup time t as 0-0-0-0-ns write pulse width t wp 12 - 15 - 17 - 20 - ns write recovery time t wr 0-0-0-0-ns write to output in high z t whz 0 10 0 12 0 15 0 15 ns data to write time overlap t dw 10 - 12 - 15 - 15 - ns data hold from write time t dh 0-0-0-0-ns output active from end of write t ow 3-3-3-3-ns -020 -025 -35 -45 parameter symbol min max min max min max min max unit read cycle time t rc 20 - 25 - 35 - 45 - ns address access time t aa - 20 - 25 - 35 - 45 ns chip select access time t acs - 20 - 25 - 35 - 45 ns output enable to output valid t oe - 10 - 12 - 15 - 17 ns output hold from address change t oh 3-3-3-3-ns chip selection to output in low z t clz 3-3-3-3-ns output enable to output in low z t olz 0-0-0-0-ns chip deselection to o/p in high z t chz 0 9 0 10 0 12 0 15 ns output disable to output in high z t ohz 0 8 0 10 0 12 0 15 ns ac operating conditions read cycle read cycle read cycle read cycle read cycle
puma 68s4000/a - 020/025/35/45 issue 4.4 : december 1999 6 read cycle timing waveform read cycle timing waveform read cycle timing waveform read cycle timing waveform read cycle timing waveform (1,2) write cycle no.1 timing waveform write cycle no.1 timing waveform write cycle no.1 timing waveform write cycle no.1 timing waveform write cycle no.1 timing waveform (1,4) t wr(7) as(6) t cw t wp(2) t dw dh aw don't care t t t t t wc ohz(3,9) address oe cs1~4 we dout din high-z high-z ow t (8) data valid oe t acs t clz (4,5) t ohz (3) t t olz aa oh chz (3,4,5) data valid t t t t rc address cs1~4 dout oe don't care. ac read characteristics notes (1) we is high for read cycle. (2) all read cycle timing is referenced from the last valid address to the first transition address. (3) t chz and t ohz are defined as the time at which the outputs achieve open circuit conditions and are not referenced to output voltage levels. (4) at any given temperature and voltage condition, t chz (max) is less than t clz (min) both for a given module and from module to module. (5) these parameters are sampled and not 100% tested.
puma 68s4000/a - 020/025/35/45 issue 4.4 : december 1999 7 write cycle no.2 timing waveform write cycle no.2 timing waveform write cycle no.2 timing waveform write cycle no.2 timing waveform write cycle no.2 timing waveform (1,5) (1,5) (1,5) (1,5) (1,5) ac write characteristics notes (1) all write cycle timing is referenced from the last valid address to the first transition address. (2) all writes occur during the overlap of cs1~4 and we low. (3) if oe, cs1~4, and we are in the read mode during this period, the i/o pins are low impedance state. inputs of opposite phase to the output must not be applied because bus contention can occur. (4) dout is the read data of the new address. (5) oe is continuously low. (6) address is valid prior to or coincident with cs1~4 and we low, too avoid inadvertant writes. (7) cs1~4 or we must be high during address transitions. (8) when cs1~4 are low : i/o pins are in the output state. input signals of opposite phase leading to the output should not be applied. (9) defined as the time at which the outputs achieve open circuit conditions and are not referenced to output voltage levels. these parameters are sampled and not 100% tested. t aw t cw wr(7) wc as(6) dw dh oh ow whz(3,9) wp(2) don't t t t t t address cs1~4 we dout din t t t t care high-z high-z (4) (8) data valid data retetnion waveform t r t cdr 4.5v 2.2v 4.5v 2.2v 0v data retention mode vcc cs1~4 v dr cs1~4 > vcc -0.2v
puma 68s4000/a - 020/025/35/45 issue 4.4 : december 1999 8 puma 68s4000/am - 020 speed 020 = 20ns 025 = 25ns 35 = 35ns 45 = 45ns temperature range blank = commercial temperature i = industrial temperature m = military temperature /we option blank = single/we a = /we1~4 memory organisation s4000 = 128k x 32 sram configurable as 256k x 16 and 512k x 8 package puma 68 = 68 pin "j" leaded plcc package information dimensions in mm(inches) plastic 68 pin jedec surface mount plcc ordering information 25.02 (0.985) sq. 25.27 (0.995) sq. (0.200) max 1.27 (0.050) typ. 0.46 (0.018) typ. 0.10 (0.004) 5.08 24.13 (0.950) 23.11 (0.910) 0.90 (0.035) typ. note : although this data is believed to be accurate the information contained herein is not intended to and does not create any warranty of merchantibility or fitness for aparticular purpose. our products are subject to a constant process of development. data may be changed without notice. products are not authorised for use as critical components in life support devices without the express written approval of a company director.
puma 68s4000/a - 020/025/35/45 issue 4.4 : december 1999 9 co planarity specified as +/- 2 thou max. visual inspection standard all devices inspected to ansi/j-std-001b class 2 standard moisture sensitivity devices are moisture sensitive. shelf life in sealed bag 12 months at <40 o c and <90% relative humidity (rh). after this bag has been opened, devices that will be subjected to infrared reflow, vapour phase reflow, or equivalent processing (peak package body temp 220 o c) must be : a : mounted within 72 hours at factory conditions of <30 o c/60% rh or b : stored at <20% rh if these conditions are not met or indicator card is >20% when read at 23 o c +/-5% devices require baking as specified below. if baking is required, devices may be baked for :- a : 24 hours at 125 o c +/-5% for high temperature device containers or b : 192 hours at 40 o c +5 o c/-0 o c and <5% rh for low temperature device containers . packaging standard devices packaged in dry nitrogen, jed-std-020. packaged in trays as standard. tape and reel available for shipment quantities exceeding 200pcs upon request. soldering recomendations ir/convection - ramp rate 6 o c/sec max. temp. exceeding 183 o c 150 secs. max. peak temperature 225 o c time within 5 o c of peak 20 secs max. ramp down 6 o c/sec max. vapour phase - ramp up rate 6 o c/sec max. peak temperature 215 - 219 o c time within 5 o c of peak 60 secs max. ramp down 6 o c/sec max. the above conditions must not be exceeded. note : the above recommendations are based on standard industry practice. failure to comply with the above recommendations invalidates product warranty.
|
